1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory, a non-volatile memory array and a manufacturing method thereof.
2. Description of Related Art
Electrically erasable programmable read only memory (EEPROM) is a type of non-volatile memory that allows multiple data reading, writing and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computer and electronic equipment.
A typical EEPROM has a floating gate and a control gate fabricated using doped polysilicon. To prevent erroneous reading resulting from the over-erasure of the EEPROM during an erasing operation, a select gate is set up above the substrate on the sidewall of the control gate and the floating gate forming a so-called split-gate structure.
At present, the industry has developed an AG–AND memory cell array fabricated using a split-gate memory cells (refer to U.S. Pat. No. 6,567,315). FIG. 1 is a schematic cross-sectional view of a portion of a conventional AG_AND memory cell structure. As shown in FIG. 1, the AG–AND memory cell structure includes a substrate 100, a well region 102, an auxiliary gate transistor Qa1 (Qa2), a memory device Qm1 (Qm2) and source/drain regions 104a, 104b (104c) in the substrate 100 on one side of the auxiliary gate transistor Qa1 (Qa2) and the memory device Qm1 (Qm2) respectively. The auxiliary gate transistor Qa1 (Qa2) includes an auxiliary gate 106a and the memory device Qm1 (Qm2) includes a floating gate 108a (108b) and a word line 110. The word line 110 serves as a control gate for the memory device Qm1 (Qm2). The auxiliary gate transistor Qa1 (Qa2) and the memory device Qm1 (Qm2) together form a memory cell Q1 (Q2). In an AG–AND array, neighboring memory cells in the row direction use a common source/drain region.
To program memory cell Q1 of the aforementioned AG–AND memory cell array, a 13V bias voltage is applied to the word line 110, a 1V bias voltage is applied to the auxiliary gate 106a, a 0V bias voltage is applied to the source/drain region 104a and a 5V bias voltage is applied to the source/drain region 104b. Thus, electrons are injected into the floating gate 108a of the memory device Qm1 to program the memory cell Q1. Because a bias voltage is not applied to the auxiliary gate 106b, the memory cell Q2 is not programmed.
However, in the aforementioned AG–AND memory cell structure, a source/drain region (104a, 104b or 104c) is formed in the substrate 100 on each side of the memory cell Q1 (Q2). To prevent the source/drain region (104a, 104b or 104c) from getting too close to the conductive channels underneath the memory cell, the source/drain regions (104a, 104b or 104c) have to be separate from each other by a definite distance. This precludes any further miniaturization of the memory cell array.